Bcdclock code code#

We could actually run it directly against an Unit test that is not influenced by an implementation. But it in any case it is better to start with a 'general' Practice there may be a good reason why a test needs to be adapted to getĮverything working. The test was run against the implementation and found to fail occasionally,Įven when the implementation was believed to be correct. Statement was not present in the first version of the test: it was added after

This is needed toĪvoid race conditions when signals change 'simultaneously' with the risingĬlock edge. Synchronizes signal changes with the falling clock edge. Think for a moment on how you would do it in Verilog or VHDL.Īlso in stimulus, note the yield clock.negedge statement. Note that it has an inner for loop over signals, asĪ concise way to define test patterns. Finally, stimulus defines a number of testĬases for the stopwatch. Is the actual test: it asserts that the actual time count from the designĮquals the expected time count. counter maintains the expected time count. The stopwatch state, based on a rising edge on either of the input signals next = LOW raise StopSimulation return dut, clkgen, action, counter, monitor, stimulus def test_bench (): sim = Simulation ( bench ()) sim. negedge # sync to avoid race condition sig. negedge ) def monitor (): assert (( tens * 100 ) + ( ones * 10 ) + tenths ) = count def stimulus (): for maxInterval in ( 100 * PERIOD, 2 * MAX_COUNT * PERIOD ): for sig in ( reset, startstop, reset, startstop, startstop, reset, startstop, startstop, startstop, reset, startstop, reset, startstop, startstop, startstop ): yield delay ( randrange ( 10 * PERIOD, maxInterval )) yield clock. next = ( count + 1 ) % MAX_COUNT ( clock. posedge ) def counter (): if counting : count. posedge ) def action (): if reset : counting. ''' tens, ones, tenths = ) for i in range ( 3 )] startstop, reset, clock = dut = TimeCount ( tens, ones, tenths, startstop, reset, clock ) count = Signal ( 0 ) counting = Signal ( False ) ( delay ( PERIOD // 2 )) def clkgen (): clock. Interface of the time counter looks as follows:įrom random import randrange from myhdl import * from TimeCount import TimeCount LOW, HIGH = bool ( 0 ), bool ( 1 ) MAX_COUNT = 6 * 10 * 10 PERIOD = 10 def bench (): ''' Unit test for time counter. The specification was described in previous sections. To write a unit test for building block, we need two things: the specificationĪnd the interface. This is of crucial importance when making design changes later on. Incomplete or invalid designs enhances the confidence in the test quality Will continue to do so until a valid implementation is achieved. This makes sure that the test writer concentrates on allĪspects of the high level specification, without being influenced by lowerĪt the start of an implementation, the existing unit test will fail, and it Moreover, the XP idea is to write the unit test first, before theĪctual implementation.

Unit testing means writing a dedicated test for each building block of aĭesign, and aggregating all tests in a regression test suite using a unit testįramework. Of unit testing, a cornerstone of extreme programming (XP). One of the goals of the MyHDL project is to promote the use of modern softwareĭevelopment techniques for hardware design. We will first design a time counter and then a bcd to led convertor. a subsystem that displays the count, by converting each bcd digit to a 7 segment led displayĪ natural partitioning often works best, and that's how we will approach theĭesign.

Bcdclock code code#

a subsystem that counts time, expressed as digits in bcd (binary coded decimal) code.tens_led: 7 segment led for most significant digit of the seconds ones_led: 7 segment led for least significant digit of the seconds tenths_led: 7 segment led for tenths of a second startstop: input that starts or stops the stopwatch on a posedge reset: reset input clock: 10Hz clock input ''' ArchitectureĪ stopwatch system is naturally partitioned as follows:

Def StopWatch ( tens_led, ones_led, tenths_led, startstop, reset, clock ): ''' 3 digit stopwatch with seconds and tenths of a second.